1. Field of the Invention
The invention relates to a digital integrated circuit comprising insulated gate field effect transistors, in which a first and a second transistor of a first conductivity type are connected on the one hand to a first feeding connection point and on the other hand to a first and a second junction, respectively, the gate electrodes of the first and of the second transistor being connected to the second and the first junction, respectively, while between a second feeding connection point and the first and the second junction, respectively, there is connected a first and a second network, respectively, of series- and/or parallel-connected transistors of the second conductivity type, whose gate electrodes receive complementary gate signals so that signal levels which are complementary to each other are produced at the first and at the second junction, respectively.
2. Description of the Related Art
In the foregoing, the term "complementary signals" includes the following: of each (gate-, output) signal which can assume a positive level of "0" (low) or "1" (high), at the same instant the complement is present as (gate-, output) signal "1" (high) or "0" (low). Such a circuit is known from Japanese Kokai No. 55-97734 published on July 25, 1980. The transistors of the first or second type are mostly P- or N-MOS transistors because then the number of P-MOS transistors is limited, as a result of which the semiconductor substrate surface area required for the circuit can also be kept limited. For the same current/voltage behaviour a P-MOS transistor requires a surface area three times larger than an N-MOS transistor because the latter has a value .beta. which is three times larger.
In principle, the circuit may be any type of logic circuit, such as a gate circuit, arithmetic circuits (inter alia full adders), decoder circuits etc.